Signal processing memos and research papers

In-depth evaluations of algorithmic pitfalls, vector optimization, and filter synthesis on constrained silicon.

FFT vector alignment

Limit-cycle mitigation

Low-latency beamforming

Strategies for cache-aligned SIMD execution when computing multi-channel 2048-point FFTs on Cortex-A cores.

In-depth analysis of fixed-point quantization noise and limit-cycle oscillations in recursive 32-bit IIR topologies.

Comparative evaluation of minimum-phase versus linear-phase cross-overs in loudspeaker dynamic limiting pipelines.

Simulation versus silicon execution

Most latency budgets break down in memory bandwidth rather than algorithmic complexity. Theoretical MATLAB simulations often assume infinite cache hits, masking cache miss penalties that derail deterministic real-time audio pipelines.

Achieving production-grade firmware requires treating instruction scheduling and memory alignment with the same mathematical rigor as filter synthesis. Zero margin remains for non-deterministic cache misses when processing multi-channel streams.

Explore custom algorithm research or obtain repositories.

Available for technical advisory, algorithmic reviews, and high-stakes signal processing engagements.